The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device with a fixed burst length including a column control circuit.
‘tAA’ refers to a time of duration between a column address strobe CAS command input and the data output in response, and as such ‘tAA’ is one main specification criteria for determining the semiconductor memory device speed. Thus, the effort to optimize ‘tAA’ continues. Smaller ‘tAA’ indicates a faster speed of a memory device as this concept is similar to the CAS latency. ‘tAA’ is determined based on the generation time of each of the CAS signal, the input and output sense amplifier control signal associated with a read operation, and the write driver control signal associated with a write operation
A main strobe signal MSTROBE, which oversees the column address selection, the input and output sense amplifier control, and the write driver control, is generated through a conventional circuit shown in FIG. 1.
Referring to FIG. 1, the conventional semiconductor memory device decodes external commands RASB, CASB, WEB, and CSB through a command decoder 100 and outputs an internal read command CASPRD and an internal write command CASPWT that are synchronized with an external clock CLK.
An address buffer 110 buffers a bank related column address ADDR to be output as a bank address CBK<0:3>.
A burst length controlling unit 120 uses a burst signal BL with burst length information to generate a burst end signal BURST_END controlling a burst operation.
The commands CASPRD and CASPWT output from the command decoder are combined through the read/write strobe pulse generating unit 130 to be output as a read/write strobe pulse signal RDWTSTBP collectively handling the read and write commands.
After decoding the bank address CBK<0:3> output from the address buffer 110 by the column decoder 140, the bank address CBK<0:3> is combined with the internal read and write commands CASPRD, and CASPWT output from the command decoder 100 to be output as a column decoding signal CASP<0:15>.
The commands CASPRD and CASPWT output from the command decoder 100, and the burst end signal BURST_END output from the burst length controlling unit 120, and the column decoding signal CASP<0:15> output from the column decoder 140, all of which are combined through a column strobe signal generating unit 150 and output as a column strobe signal CAST<0:15> having the command information, the bank address information, and the burst length information.
A main strobe signal generating unit 160 uses the read write strobe pulse signal RDWTSTBP output from the read/write strobe pulse generating unit 130 and the column strobe signal CAST<0:15> output from the column strobe signal generating unit 150 to generate a main strobe signal MSTROBE<0:15>.
And, the main strobe signal MSTROBE<0:15> generated from the main strobe signal generating unit 160 is input to a corresponding bank 170 to collectively handle the column address selection, the input and output sense amplifier control, and the write driver control.
As above, the conventional semiconductor memory device generates the main strobe signal MSTROBE<0:15> by combining the column strobe signal CAST<0:15> (which is a combination of the burst end signal BURST_END and the column decoding signal CASP<0:15>) and the read/write strobe pulse signal RDWTSTBP (which handles the read and write commands).
In other words, the read/write strobe pulse generating unit 130, the column decoder 140, the column strobe signal generating unit 150, and the main strobe signal generating unit 160 are required in a conventional semiconductor memory device in order to generate the main strobe signal MSTROBE<0:15>.
This increases circuit areas in the conventional semiconductor memory device to provide spaces for the circuits 130, 140, 150, 160. These circuits 130, 140, 150, 160 generate a plurality of signals in order to generate the main strobe signal MSTROBE<0:15>, and this causes the total time for generating the main strobe signal MSTROBE<0:15> to increase.
In particular, it is possible that the signals from the circuits 130 to 160 that are to be combined may not be input to the corresponding circuits at the same point in time for combination, and in anticipation of these possibilities each of the circuits 130 to 160 additionally require delay elements such as an inverter, etc. in order to compensate for the delay of the signals.
These additional delay elements will cause the area of the semiconductor memory device to increase additionally, and further the time required for generating the main strobe signal MSTROBE<0:15> will also increase due to the signal delays caused by the added delay elements. This is problematic in that the ‘tAA’ will increase if the generation time of the main strobe signal MSTROBE<0:15> increase.
Also, the design trends for the high speed semiconductor memory devices call for a fixed burst length rather than a variable burst length. Accordingly, applying the conventional circuits 130, 140, 150, 160 in the design of a fixed burst length memory device would waste the circuit area of the semiconductor memory device and increase the generation time of the main strobe signal MSTROBE<0:15>.
In other words, high speed semiconductor memory devices will likely utilize the fixed burst length, there is no need for the circuit areas occupied by the unnecessary circuits for controlling the burst length that will also cause the ‘tAA’ to increase as the generation time of the main strobe signal MSTROBE<0:15> increase.